A Framework for Embedded Ferroelectric Memory Development
June 12 (Thursday), 2025
11:30 am to 12:30 pm (EDT)
Virtual via Zoom
Abstract: An overview of the steps employed to advance non-volatile Pb(ZrxTi1-x)O3-based memory components from parallel capacitor array test structures to an embedded 130 nm (1.5 V operation) memory product release is presented. Specific development stages include parallel capacitor array evaluation, capacitor characterization array development, memory macro creation and measurement, and initial product design and qualification. Representative data, learning goals, and critical outputs will be presented for each development phase. We note that the cost and complexity of the development effort increase dramatically as the new technology approaches high-volume manufacturing.
Biography: Dr. Ted Moise is Research Professor within the Materials Science Department at the University of Texas at Dallas, and also serves as the Director of the North Texas Semiconductor Institute. He earned a B.S. degree from Trinity College and a Ph.D. degree from Yale University. In 1997, Ted and his team started work on the development of scaled ferroelectric capacitors leading to the industry’s first production of low-voltage, high-density, embedded ferroelectric random-access memory (FRAM). Texas Instruments and its partners have designed and sold FRAM-based products into a wide range of applications. From 2007-2021, Ted led several technology development and product engineering teams at Texas Instruments. In 2022, Ted joined the University of Texas at Dallas. Ted is an IEEE Fellow and a Fellow of the National Academy of Inventors.