Innovations to Enable Future Logic Scaling
September 9 (Thursday), 2021
11:30 am to 12:30 pm (EDT)
Virtual via Zoom
Abstract: Logic scaling over the last 50 years has been enabled by patterning innovations, mobility boosters and new device architectures. In the recent nodes, transistor density continues to follow Moore’s law, but the node to node performance improvements have slowed down. There are many new process technologies being researched which will continue to enable logic density and system performance in the coming decade. Density scaling will be enabled by advances in EUV multi-patterning and single-print high NA EUV. New device architectures like forksheets, CFETs and 2D atomic channel devices are promising for continued logic and SRAM scaling. Scaling boosters like buried power rail, semi-damascene integration and new standard cell routing will also be needed. There are several 2.5D and 3D integration options for system scaling with SoC partitioning depending on the connectivity density, form factor, yield, maturity and cost considerations. Finally, a methodology to estimate the environmental impact of technology scaling choices will be shared.
Biography: Sri Samavedam is SVP of CMOS Technologies at imec leading research programs in logic, memory, photonics and 3D system integration. Prior to that, he was Senior Director of Technology Development at Globalfoundries in Malta, NY, where he led qualification of 14nm FinFET technology and derivatives into volume production and development of 7nm CMOS technology. He began his research career at Motorola in Austin, TX, working on strained silicon, metal gates, high k dielectrics and fully-depleted SOI devices. He has over 75 publications and 40 patents. He holds a Ph.D. in Materials Science and Engineering from MIT, Masters in Materials Engineering from Purdue University and B. Tech from IIT, Madras.